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Welcome to the exciting world of embedded systems. We have prepared a series of labs for this course to give you hands-on experience in Hardware/Software Co-design. Each lab consists of two parts: 1) the first part consists of a tutorial with step-by-step guidance and 2) the second part is an assignment to allow students to use practical knowledge gained from the first part to solve a fairly simple design and implementation problem.

Lab Venue : Online

Lab Info

Lab Description
1Introduction to Hardware Design7%

Introduction to Hardware/Software Co-design

3Integrating the Co-processor7%
4High-Level Synthesis7%
5Mini Project


2% for Progress Evaluation

20% for Final Demo

Lab Schedule


Date (Week of)




24 Jan 2022

Lab 1 Intro


31 Jan 2022

Lab 1 Demo/Consultation, Lab 2 Intro

Lab 1 can be demonstrated in Week 4 or 5.


7 Feb 2022

Lab 1 Demo, Lab 2 Consultation

Lab 1 can be demonstrated in Week 4 or 5.


14 Feb 2022

Lab 2 Demo, Lab 3 Intro

RecessNo sessionWork on Lab 3
728 Feb 2022Lab 3 Demo, Lab 4 Intro
87 Mar 2022Project Intro
914 Mar 2022Lab 4 Demo, Project Consultation
1021 Mar 2022Project Consultation
1128 Mar 2022Project Progress Evaluation and Consultation
124 Apr 2022Project Demo
ZED Board

You will be provided a ZED board containing a Xilinx Zynq chip. More information about the board can be found below.

ZedBoard™ is a complete development kit for designers interested in exploring designs using the Xilinx Zynq®-7000 All Programmable SoC. The board contains all the necessary interfaces and supporting functions to enable a wide range of applications. The expandability features of the board make it ideal for rapid prototyping and proof-of-concept development.

More details about the board and some reference designs can be found on the link below:

ZED site


Late demo / submission policy

For each assessment, you must demonstrate on the stipulated date during your schedule time slot as given in the assessment schedule. If you don't, you get a 0 mark for that lab! You are supposed to submit your codes to IVLE by the deadline for uploading - if you submit after the deadline, you will be given a 10% discount in marks. A late demo is allowed (with no penalty) only if you are able to produce a documented evidence to justify the late demo/submission - in such a case, please let us know immediately as and when such a situation arises.

Email policy

Kindly DO NOT send emails regarding labs wherever possible. Post them on the wiki. Only if the matter is personal / administrative, please email [rajesh<>].

Plagiarism Warning

It might be tempting to 'refer' to the code found in the textbook / online sources. However, please note that we take dishonesty very very seriously. If we are confident that you did plagiarize, you might not even be given a chance to explain. Consequences can range from an unpleasant surprise on the day of release of results to having an interview with the NUS board of discipline.

If you think renaming variables / rearranging code helps circumvent plagiarism detection, you might want to read this -

Discussions are encouraged, but 'we had discussed' is not a valid excuse if your codes turn out to be uncomfortably similar. 

Though there will be intra-team differentiation in marks according to the contribution levels, a team will be collectively responsible for plagiarized code. Your teammates might be better off with no contribution at all from you than to receive plagiarized code.   



 : Lab schedule updated.


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