Information
Welcome to the exciting world of embedded systems. We have prepared a series of labs for this course to give you hands-on experience in Hardware/Software Co-design. Each lab consists of two parts: 1) the first part consists of a tutorial with step-by-step guidance and 2) the second part is an assignment to allow students to use practical knowledge gained from the first part to solve a fairly simple design and implementation problem.
Lab Venue : Digital Electronics Lab
Lab Info
Lab Description
| Lab | Description | Weight | Remarks |
|---|---|---|---|
| 1 | Introduction to Hardware Design | 7% | |
| 2 | Introduction to Hardware/Software Co-design | 7% | |
| 3 | Integrating the Co-processor | 7% | |
| 4 | High-Level Synthesis | 7% | |
| 5 | Mini Project | 22% | 2% for Progress Evaluation 20% for Final Demo |
Lab Schedule
Week | Date | Activity | Remarks |
|---|---|---|---|
3 | 24 Jan 2022, 27 Jan 2023 | Lab 1 Intro | |
4 | 31 Jan 2023, 3 Feb 2023 | Lab 1 Demo/Consultation, Lab 2 Intro | Lab 1 can be demonstrated in Week 4 or 5. |
5 | 7 Feb 2023, 10 Feb 2023 | Lab 1 Demo, Lab 2 Consultation | Lab 1 can be demonstrated in Week 4 or 5. |
6 | 14 Feb 2023, 17 Feb 2023 | Lab 2 Demo, Lab 3 Intro | |
| Recess | No session | Work on Lab 3 | |
| 7 | 28 Feb 2023, 3 Mar 2023 | Lab 3 Demo, Lab 4 Intro | |
| 8 | 7 Mar 2023, 10 Mar 2023 | Project Intro | |
| 9 | 14 Mar 2023, 17 Mar 2023 | Lab 4 Demo, Project Consultation | |
| 10 | 21 Mar 2023, 24 Mar 2023 | Project Progress Evaluation and Consultation | |
| 11 | 28 Mar 2023, 31 Mar 2023 | Project Consultation | |
| 12 | 4 Apr 2023, 7 Apr 2023 | Project Demo |
ZED Board
You will be provided a ZED board containing a Xilinx Zynq chip. More information about the board can be found below.
ZedBoard™ is a complete development kit for designers interested in exploring designs using the Xilinx Zynq®-7000 All Programmable SoC. The board contains all the necessary interfaces and supporting functions to enable a wide range of applications. The expandability features of the board make it ideal for rapid prototyping and proof-of-concept development.
More details about the board and some reference designs can be found on the link below:
* ZED site
Policies
Late demo / submission policy
For each assessment, you must demonstrate on the stipulated date during your schedule time slot as given in the assessment schedule. If you don't, you get a 0 mark for that lab!
You are supposed to submit your codes to Canvas by the deadline for uploading - if you submit after the deadline, you will be given a 10% discount in marks. You are expected to submit the exact same code used for evaluation - any bug fixes/improvements after the demo could you useful for future labs and project, but will not result in an increase in marks after the demo.
A late demo is allowed (with no penalty) only if you are able to produce documented evidence to justify the late demo/submission - in such a case, please let us know immediately as and when such a situation arises.
Email policy
Kindly DO NOT send emails regarding labs wherever possible. Post them on the wiki. Only if the matter is personal / administrative, please contact the lecturer via Canvas Inbox (not emails).
Plagiarism Warning
It might be tempting to 'refer' to the code found in the textbook / online sources. However, please note that we take dishonesty very very seriously. If we are confident that you did plagiarize, you might not even be given a chance to explain. Consequences can range from an unpleasant surprise on the day of the release of results to having an interview with the NUS board of discipline.
If you think renaming variables / rearranging code helps circumvent plagiarism detection, you might want to read this - http://en.wikipedia.org/wiki/Plagiarism_detection#In_source_code.
Discussions are encouraged, but 'we had discussed' is not a valid excuse if your codes turn out to be uncomfortably similar.
Though there will be intra-team differentiation in marks according to the contribution levels, a team will be collectively responsible for plagiarized code. Your teammates might be better off with no contribution at all from you than to receive plagiarized code.
Updates
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: Lab schedule updated.
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4 Comments
Chatterjee Anurag
Hi Prof, where will the lab be held tmrw?
Rajesh Chandrasekhara Panicker
Digital Electronics Lab, E4-03-07. You can see more details in the email the lab officer sent today.
Xue Yao
Just wanted to share some consumer electronics that makes use of FPGA that I think is pretty interesting:
https://www.analogue.co/pocket
This is a game console that can emulate multiple retro devices, through FPGA. The devs reverse-engineered as much of the older consoles (Gameboy etc) as possible and wrote the FPGA cores to emulate these devices to perfection. It's a super cool and nerdy device.
https://www.crowdsupply.com/sutajio-kosagi/precursor
This is designed to be an extremely secure device, meant to be the be-all-end-all digital equivalent of your key chain. It can run a whole host of application, from password manager, OTP, U2F, SSH/PGP keys, mnemonics phrases etc. To guarantee software and hardware security, the devs designed this to run on an FPGA so that even the CPU architecture and design can be verified and even replaced by the end user. This completely sidesteps the closed source nature of popular chip designs such as ARM or X86. Super cool device and is actually close to being semi-useful and a great alternative to Yubikeys and hardware wallets.
Rajesh Chandrasekhara Panicker
Cool, thanks a lot for sharing :)